FPGA based modified multi-repeat distribution matcher for probabilistic amplitude shaping
DOI:
https://doi.org/10.5377/nexo.v36i05.17298Keywords:
FPGA, MMRDM, MIMO, ZERO-FORCED, MMSE, Xilinx System GeneratorAbstract
The technique of probabilistic amplitude modulation, based on distribution matching, has garnered considerable attention in recent years as a means to enhance spectral efficiency and diminish the constellation energy of coded modulation. This paper introduces the implementation of Probabilistic Amplitude Modulation (PAS) using a Modified Multi-Repeat Distribution Matcher (MMRDM) on a Field Programmable Gate Array (FPGA). The Modified Multiple Repetition Distribution Matcher (MMRDM) is integrated into a 2×2 Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) system, realized through the Xilinx System Generator (XSG). Simple Zero-Forced and Minimum Mean Squared Error (MMSE) equalizers are applied to the receiver for signal detection across the MIMO channel. The system incorporates enhanced security through chaos-based scrambling with 16 and 64 Quadrature Amplitude Modulation (QAM). VHDL code files for this system are generated for the Xilinx Kintex-7 (xc7k325t-3fbg676) for hardware implementation. Performance evaluation includes an assessment of required storage capacity, complexity, and bit error rate (BER). Using Vivado 2017.4, the system is successfully routed with resource utilization, for example, 0.67% Block RAM (BRAM), 68.6% Look-Up Tables (LUT), 83% DSP 48s, and 1.5% registers for 64-QAM uniform modulation. Similarly, for 64-QAM 10 level (shaper output 60 bit) shaped modulation, the resource utilization is 0.67% BRAM, 68.8% LUT, 83% DSP 48s, and 1.6% registers on the specified device. Simulation results demonstrate an improvement in the net shaping gain of approximately (2-4 dB) at 1×10^(-4) for different equalizer cases compared to uniform QAM, along with a notable reduction in required storage capacity and computational complexity.
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